Integrated circuits (IC) containing decoupling capacitors are commonly employed in virtually all modern electronic systems. Decoupling capacitors are typically mounted between power and ground circuits to ensure stable power to the IC. For the purposes of the present invention an integrated circuit may be a discrete element, a package of multiple discrete elements, or it may be incorporated into an integrated circuit package wherein the IC package comprises additional functioning elements.
The location of decoupling capacitors has become increasingly more important as the clock speed, or switching frequencies, of modern IC's has increased. With low clock speeds, such as hundreds of kilohertz to tens of megahertz, the location is of less significance. As clock speeds approach hundreds of megahertz or higher it becomes imperative to minimize the inductance of the decoupling circuit traces such that parasitic inductance is minimized. Parasitic inductance has been reduced markedly by optimization of the component design, as well as positioning of the decoupling capacitors nearer to the IC and with use of smaller capacitors having lower inductance values. As clock speeds increase further these prior improvements will be less suitable for high speed decoupling as the associated parasitic inductances associated with these methods has largely been minimized.
Capacitive interposers situated between the IC and printed circuit board (PCB) have improved the parasitic inductance as indicated in U.S. Pat. Nos. 6,961,231 and 7,268,419. A capacitive interposer has an array of connectors on each surface. The IC, or IC package, is coupled to the interposer at the lands on one surface of the interposer. The PCB is coupled to the capacitive interposer at lands on the opposite side of the interposer. Electrically conductive vias in the capacitive interposer interconnect the lands with terminals on the opposite side. Capacitors are mounted on, or incorporated into, the capacitive interposer thereby providing the decoupling function desired.
Capacitive interposers are described throughout the literature as exemplified in U.S. Pat. Nos. 7,123,465 and 6,891,258 and U.S. Pat. Publ. Nos. 2007/0065983 and 2006/0012966. While these provide a savings in total circuit space the function contained therein is limited to capacitance and decoupling. Methods for combining elements to increase special efficiency are provided throughout the literature yet these are typically combinations of elements and the manufacturing cost of such elements is prohibitive. Exemplary references include U.S. Pat. Nos. 7,084,501; 7,006,359; 6,963,493 and 5,475,262.
Capacitive interposers are relatively thin and typically do not add significantly to the overall volume of the electronic package. It is typical in the electronics industry that each generation of advancement in electronic devices demands higher clock speeds, smaller size and increased functionality. This ongoing demand requires even further reduction in size, increased functionality as well as decreases in parasitic inductance.